Struct raw_cpuid::ProcessorCapacityAndFeatureInfo

pub struct ProcessorCapacityAndFeatureInfo { /* private fields */ }

Processor Capacity Parameters and Extended Feature Identification (LEAF=0x8000_0008).

This function provides the size or capacity of various architectural parameters that vary by implementation, as well as an extension to the 0x8000_0001 feature identifiers.

Platforms

✅ AMD 🟡 Intel

Implementations

impl ProcessorCapacityAndFeatureInfo

pub fn physical_address_bits(&self) -> u8

Physical Address Bits

Platforms

✅ AMD ✅ Intel

pub fn linear_address_bits(&self) -> u8

Linear Address Bits

Platforms

✅ AMD ✅ Intel

pub fn guest_physical_address_bits(&self) -> u8

Guest Physical Address Bits

This number applies only to guests using nested paging. When this field is zero, refer to the PhysAddrSize field for the maximum guest physical address size.

Platforms

✅ AMD ❌ Intel (reserved=0)

pub fn has_cl_zero(&self) -> bool

CLZERO instruction supported if set.

Platforms

✅ AMD ❌ Intel (reserved=false)

pub fn has_inst_ret_cntr_msr(&self) -> bool

Instruction Retired Counter MSR available if set.

Platforms

✅ AMD ❌ Intel (reserved=false)

pub fn has_restore_fp_error_ptrs(&self) -> bool

FP Error Pointers Restored by XRSTOR if set.

Platforms

✅ AMD ❌ Intel (reserved=false)

pub fn has_invlpgb(&self) -> bool

INVLPGB and TLBSYNC instruction supported if set.

Platforms

✅ AMD ❌ Intel (reserved=false)

pub fn has_rdpru(&self) -> bool

RDPRU instruction supported if set.

Platforms

✅ AMD ❌ Intel (reserved=false)

pub fn has_mcommit(&self) -> bool

MCOMMIT instruction supported if set.

Platforms

✅ AMD ❌ Intel (reserved=false)

pub fn has_wbnoinvd(&self) -> bool

WBNOINVD instruction supported if set.

Platforms

✅ AMD ✅ Intel

pub fn has_int_wbinvd(&self) -> bool

WBINVD/WBNOINVD are interruptible if set.

Platforms

✅ AMD ❌ Intel (reserved=false)

pub fn has_unsupported_efer_lmsle(&self) -> bool

EFER.LMSLE is unsupported if set.

Platforms

✅ AMD ❌ Intel (reserved=false)

pub fn has_invlpgb_nested(&self) -> bool

INVLPGB support for invalidating guest nested translations if set.

Platforms

✅ AMD ❌ Intel (reserved=false)

pub fn perf_tsc_size(&self) -> usize

Performance time-stamp counter size (in bits).

Indicates the size of MSRC001_0280[PTSC].

Platforms

✅ AMD ❌ Intel (reserved=false)

pub fn apic_id_size(&self) -> u8

APIC ID size.

A value of zero indicates that legacy methods must be used to determine the maximum number of logical processors, as indicated by CPUID Fn8000_0008_ECX[NC].

Platforms

✅ AMD ❌ Intel (reserved=0)

pub fn maximum_logical_processors(&self) -> usize

The size of the apic_id_size field determines the maximum number of logical processors (MNLP) that the package could theoretically support, and not the actual number of logical processors that are implemented or enabled in the package, as indicated by CPUID Fn8000_0008_ECX[NC].

MNLP = (2 raised to the power of ApicIdSize[3:0]) (if not 0)

Platforms

✅ AMD ❌ Intel (reserved=0)

pub fn num_phys_threads(&self) -> usize

Number of physical threads in the processor.

Platforms

✅ AMD ❌ Intel (reserved=0)

pub fn invlpgb_max_pages(&self) -> u16

Maximum page count for INVLPGB instruction.

Platforms

✅ AMD ❌ Intel (reserved=0)

pub fn max_rdpru_id(&self) -> u16

The maximum ECX value recognized by RDPRU.

Platforms

✅ AMD ❌ Intel (reserved=0)

Trait Implementations

impl Debug for ProcessorCapacityAndFeatureInfo

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl PartialEq for ProcessorCapacityAndFeatureInfo

fn eq(&self, other: &ProcessorCapacityAndFeatureInfo) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Eq for ProcessorCapacityAndFeatureInfo

impl StructuralPartialEq for ProcessorCapacityAndFeatureInfo